In accordance with the complexity and variety of systems, the number of processors on one integrated circuit also increases. The processors exchange data using a common bus as shown in FIG. 1.
FIG. 1 illustrates a conventional integrated circuit using a common bus.
When a single integrated circuit includes four processors 100-1 through 100-4 as shown in FIG. 1, the processors 100-1 through 100-4 exchange data using one common bus 120. The integrated circuit controls the processors 100-1 through 100-4 to exchange data by sharing the common bus 120 using an arbiter 110. For example, to transfer data to the second processor 100-2, the first processor 100-1 requests use of the common bus 120 from the arbiter 110.
The arbiter 110 checks status of the common bus 120. Upon determining that the first processor 100-1 can use the common bus 120, the arbiter 110 sends a bus permission signal to the first processor 100-1.
Upon receiving the bus permission signal from the arbiter 110, the first processor 100-1 transfers data to the second processor 100-2 through the common bus 120.
However, when the number of processors on one integrated circuit increases, the integrated circuit is not able to support a bandwidth required by the processors using a single common bus.
To address this problem, research was conducted on a Network on Chip (NoC), which separates a processing block and a communication circuit. Herein, the NoC separates the processing block and the communication circuit as shown in FIG. 2.
FIG. 2 illustrates a conventional NoC of the system on chip.
The NoC of FIG. 2 includes processing elements (PEs) 200-1 to 200-8 which are an on-chip device, network interfaces 210-1 to 210-8 for interconnecting PEs 200 with a network, switches 220-1 to 220-8, and links 230. Herein, links 230, which are bidirectional links, interconnect a network interface 210 with a switch 220 or a switch 220 with another switch 220.
In the NoC structure, the PEs 200 transfer data only in the link selected by the switch 220. For instance, to transfer data from the first PE 200-1 to the fifth PE 200-5, the first switch 220-1 connected to the first PE 200-1 selects the link connected to the fifth switch 220-5. Hence, the first PE 200-1 transfers data to the fifth PE 200-5 through the link between the first switch 220-1 and the fifth switch 220-5.
As above, since the PEs 200 transfer data in the link selected by the switch 220, multiple data can be transmitted at the same time over the non-overlapping links. Therefore, the NoC structure can provide a high transfer bandwidth.
The frequency of the PEs on the NoC is designated according to their task. The PEs have different frequencies respectively. In other words, as the PEs require different frequencies, drawing a single voltage causes unnecessary power consumption. The PEs can reduce power consumption by drawing the optimum voltage based on their required frequency. Also, based on the different operation time, the PEs can lower power consumption by cutting the power supply to non-operating PEs.
However, since the switches in the NoC need to select the link to the destination among their connected links according to the request of the PE, voltage is supplied to all of the links of the NoC at all times. In this situation, unnecessary power consumption is caused by the voltage supplied to links which do not transfer data.